1. 28 May, 2020 3 commits
    • Eugen Hristev's avatar
      Makefile: prepare 3.9.3 · d96833a4
      Eugen Hristev authored
      
      Signed-off-by: default avatarEugen Hristev <eugen.hristev@microchip.com>
      d96833a4
    • Eugen Hristev's avatar
      README: update windows instructions to use python3 · 3b915bd9
      Eugen Hristev authored
      
      
      The following section in README.txt needs to be updated.
      installing
      python3 vs python2, the symlinks aren't required anymore, it seems.
      
            $ pacman -S bc gawk gcc git make python2 tar
            $ cd /usr/bin
            $ ln -s python2.exe python.exe && ln -s python2-config
      python-config
      
      Further comments about this change: considering that macOS 10.8 to
      10.15 come with Python 2.7 preinstalled (as /usr/bin/python2.7 and
      /usr/bin/python), out-of-the-box user experience will be affected on
      this OS. Not a big deal for CLI users, but for IDE users (MPLAB),
      maybe we'll consider modifying the Makefile so that it tests for
      python3 availability, and fallbacks to python2 or python, when it calls
      scripts/addpmecchead.py (bypassing the shebang).
      
      Because the 'python' package, on Windows with Minimal SYStem 2,
      provides Python 3.7 as /usr/bin/python3 (and as /usr/bin/python too).
      
      macOS 10.13 with MacPorts can achieve the same:
           port install python38
           port select --set python3 python38
           port select --set python python38
      
      Debian also offers the flexibility to select the default Python version:
           update-alternatives --install /usr/bin/python python /usr/bin/python3.8
      
      And Fedora too:
           alternatives --install /usr/bin/python python /usr/bin/python3.8
      Suggested-by: default avatarAubin Constans <aubin.constans@microchip.com>
      Signed-off-by: default avatarEugen Hristev <eugen.hristev@microchip.com>
      3b915bd9
    • Codrin Ciubotariu's avatar
      scripts: upgrade scripts to use Python3 · 58dd441c
      Codrin Ciubotariu authored
      
      
      python command no longer exists in some build systems. Use python3
      instead. Mention dependency in README.
      Signed-off-by: default avatarCodrin Ciubotariu <codrin.ciubotariu@microchip.com>
      58dd441c
  2. 22 May, 2020 1 commit
  3. 14 May, 2020 1 commit
  4. 22 Apr, 2020 1 commit
  5. 06 Apr, 2020 2 commits
  6. 30 Mar, 2020 4 commits
  7. 25 Mar, 2020 2 commits
  8. 06 Mar, 2020 1 commit
  9. 16 Jan, 2020 1 commit
    • Aubin Constans's avatar
      board: sama5d2, sama5d4: grant non-secure access to the DDR AESB CS address space · 5a3157e7
      Aubin Constans authored
      
      
      DDR2 Port 0 is the port connected to the AESB Bridge.
      Writing data to the DDR AESB Chip Select address space is the way to
      write data to external RAM, with the AESB encrypting it on the fly and
      transparently.
      
      As done already for the other DDR2 Ports (1 to 7), in the 64-bit AHB
      Matrix, configure the DDR2 Port 0 slave so that its 4 equally-sized
      regions cover the full memory space of on-board DDR-SDRAM.
      As an example, boards equipped with 512 MiB DDR-SDRAM configure 128 MiB
      per region.
      
      All 4 regions are entirely configured for Non-secure access.
      
      Before this change, DDR2 Port 0 was typically assigned 1 MiB-sized
      slave regions. Deep accesses into the DDR AESB Chip Select address
      space (beyond its base address plus a 4 MiB offset) were hitting the
      Access Denied Area of this slave.
      Signed-off-by: default avatarAubin Constans <aubin.constans@microchip.com>
      5a3157e7
  10. 15 Jan, 2020 3 commits
  11. 14 Jan, 2020 7 commits
    • Vladimir Petrigo's avatar
      board: sama5d4_xplained: update SAMA5D4 Xplained MCI definition · fd9b06b8
      Vladimir Petrigo authored
      
      
      Originally, according to the Xplained board UG, an SD card is connected to MCI1 interface
      Signed-off-by: default avatarVladimir Petrigo <taenaru@gmail.com>
      fd9b06b8
    • Eugen Hristev's avatar
      Config: MEM_BANK and MEM_SIZE are not kernel-loading dependant · 5901c1f2
      Eugen Hristev authored
      
      
      We need to be able to set MEM_BANK , MEM_BANK2 and MEM_SIZE
      regardless of the fact that we load the Linux Kernel directly or not.
      The size of the ext RAM and start of ext RAM can be used by other drivers.
      For example, trustzone requires this information.
      Signed-off-by: default avatarEugen Hristev <eugen.hristev@microchip.com>
      5901c1f2
    • Eugen Hristev's avatar
      crt0_gnu.S: configure VBAR at reset vector · be746561
      Eugen Hristev authored
      
      
      In sama SoCs, the SRAM is mapped at CONFIG_LINK_ADDR.
      This means the reset vectors are at address CONFIG_LINK_ADDR considering
      how at91bootstrap is currently linked
      The RomCode may remap SRAM at address 0x0 before jumping to at91bootstrap.
      This is why the reset vectors are actually used correctly: they are also
      available at 0x0 address (for all sama5 devices).
      However this leads to jumping to the 'mirror' of the SRAM in case of
      exceptions.
      We have to make sure that we keep the CONFIG_LINK_ADDR config valid in all
      circumstances, and configure the Core with this link address as a base for
      reset vectors.
      By configuring CP15 and VBAR, we can achieve this, the fact that the
      reset vectors are actually at CONFIG_LINK_ADDR.
      Signed-off-by: default avatarEugen Hristev <eugen.hristev@microchip.com>
      be746561
    • Dan Sneddon's avatar
      defconfig: sama5d2_xplained: bkpt + noload · 185abe0a
      Dan Sneddon authored
      
      
      Create defconfig for building for the sama5d2_xplained with bkpt support
      for use with loading application images via debuggers.
      Signed-off-by: default avatarDan Sneddon <daniel.sneddon@microchip.com>
      185abe0a
    • Dan Sneddon's avatar
      Config.in: Add bkpt for debugger notification · 0100340d
      Dan Sneddon authored
      In order to debug images built for DRAM on the A5D2 using certain IDE's
      we need to have at91bootstrap configured to set-up the clocks and
      memories correctly but notify the debugger by setting a breakpoint
      instead of loading and jumping to the image.
      
      Signed-off-by: Dan Sneddon <daniel.sneddon@microchip.com
      0100340d
    • Eugen Hristev's avatar
      crt0_gnu.S: use #ifdef CONFIG_PMC_COMMON for lowlevel_clock_init · 9d3e1363
      Eugen Hristev authored
      This call needs to be under #ifconfig for CONFIG_PMC_COMMON
      
      Otherwise platforms not having either PMC_V1 nor PMC_V2 will fail build
      
      Fixes: 463676e7
      
       ("driver: add Kconfig for PMC, PIO, USART, WDT, RSTC")
      Signed-off-by: default avatarEugen Hristev <eugen.hristev@microchip.com>
      9d3e1363
    • Eugen Hristev's avatar
      driver: at91_slowclk: implement returning to internal RC · d9ebb82d
      Eugen Hristev authored
      We can have the following scenario:
      1) Boot the board with at91bootstrap that has CONFIG_SCLK enabled.
       It will configure the external slow oscillator.
      2) Reset board, or power down, replug.  Replace at91bootstrap with an
       at91bootstrap that has CONFIG_SCLK disabled.
       According to the at91boostrap help, this means use internal RC.
        Thus, at91boostrap will not touch this register (SLOW_CLOCK.SCKR)
      3) Result is that the external slow clock crystal is still in use.
       Not touching SCKR , combined with battery-backed configuration means
       that the old config is still in effect.
      
      This fix solves that.
      CONFIG_SCLK is now part of a choice menu: either CONFIG_SCLK=y, or
      CONFIG_SCLK_INTRC=y. When booting with CONFIG_SCLK=n, it will call the
      function to go back to internal RC. When booting with CONFIG_SCLK=y it will
      enable the external slow clock.
      If the SoC has no slow clock whatsoever, there will be none of CONFIG_SCLK
      and CONFIG_SCLK_INTRC thus no code is ca...
      d9ebb82d
  12. 13 Jan, 2020 1 commit
  13. 29 Nov, 2019 1 commit
  14. 28 Nov, 2019 1 commit
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  16. 22 Oct, 2019 1 commit
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  19. 09 Oct, 2019 3 commits
  20. 08 Oct, 2019 1 commit
  21. 02 Oct, 2019 2 commits
  22. 19 Sep, 2019 1 commit